1. Field of the Invention
The present invention relates to methods for fabricating semiconductor devices each having a silicided region, and more particularly relates to semiconductor devices containing nickel silicide and methods for fabricating the same.
2. Description of Related Art
In recent years, with miniaturization of semiconductor devices, the minimum feature sizes of semiconductor devices have reached the deep submicron level, e.g., 50 nm. However, there have occurred, as one of factors that interfere with miniaturization of semiconductor devices, problems that interfere with an increase in performance of integrated circuits, such as a decrease in circuit speeds due to an increase in the resistance of a gate electrode caused by making the gate electrode finer. To cope with this, the following method is often used: The top surface of a polycrystalline polysilicon film forming part of a gate electrode of a field-effect transistor (FET) is subjected to metal silicidation for the purpose of suppressing an increase in the resistance of the gate electrode caused by making the gate electrode finer and thus the resistance of the gate electrode is reduced.
However, a metal silicide film becomes more likely to be broken due to silicide agglomeration with a reduction in its line width. It has been reported that in particular, in the case of a gate electrode having a dual-gate structure, a metal silicide film formed by siliciding a polycrystalline silicon film is increasingly likely to be broken at the PN junction of the polycrystalline silicon film. The dual-gate structure herein means a structure in which a single gate electrode has both a P-type part and an N-type part. Variations in the impurity concentration at the PN junction are considered as one of factors why a metal silicide film is likely to be broken at the PN junction of the polycrystalline silicon film.
In a case where a metal silicide film is broken at the PN junction, there occurs a serious problem that the resistance of a gate electrode is extremely increased when the PN junction is reverse-biased. To cope with this, there has been suggested a semiconductor device fabrication method for avoiding an increase in the resistance of a gate electrode due to such a broken film.
A schematic plan structure of a gate electrode illustrated in FIG. 7 is disclosed, for example, in Japanese Unexamined Patent Publication No. 2001-77210 (hereinafter, referred to as “Document 1”). In this structure, a part of a gate electrode located in the vicinity of the interface 13 between an N-type region 11 of a substrate and a P-type region 12 thereof has a larger width than the other part thereof. This restrains part of a metal silicide film from being broken at the PN junction.
Furthermore, another technique for restraining a metal silicide film from being broken at the PN junction is disclosed in Japanese Unexamined Patent Publication No. 2005-129615 (hereinafter, referred to as “Document 2”). This technique will be described with reference to FIGS. 8A through 8E.
First, as illustrated in FIG. 8A, a silicon substrate 21 is partitioned by its isolation region 22, and a gate insulating film 23 is formed on the top surface of the silicon substrate 21. Furthermore, a polycrystalline silicon film 24 is formed on the gate insulating film 23. Some of regions of the silicon substrate 21 defined by the isolation region 22 are represented as N-type FET regions 25 at which N-channel type field-effect transistors are formed, and the other ones of the regions are represented as P-type FET regions 26 at which P-channel type field effect transistors are formed.
Next, as illustrated in FIG. 8B, a resist 27 is formed on a part of a polycrystalline silicon film 24 located on the P-type FET region 26. Subsequently, phosphorus ions representing an N-type impurity are implanted into a part of the polycrystalline silicon film 24 located on the N-type FET region 25 using the resist 27 as a mask. Moreover, as illustrated in FIG. 8C, the resist 27 formed on the P-type FET region 26 is removed, and then a resist 28 is formed on the part of the polycrystalline silicon film 24 located on the N-type FET region 25. Subsequently, boron ions representing a P-type impurity are implanted into the part of the polycrystalline silicon film 24 located on the P-type FET region 26.
The conditions under which phosphorus and boron ions are implanted into the associated parts of the polycrystalline silicon film 24, respectively, are set such that the location at which the concentration of the implanted boron in the polycrystalline silicon film 24 reaches its peak becomes closer to the top surface of the silicon substrate 21 than the location at which the concentration of the implanted phosphorus therein reaches its peak. This prevents a PN junction 29 formed in the polycrystalline silicon film 24 from coinciding with the interface 29a between the top surface of a part of the polycrystalline silicon film 24 located on the P-type FET region 25 and the top surface of a part thereof located on the N-type FET region 26.
Thereafter, as illustrated in FIG. 8D, the resist 28 is removed, and then a metal film 30 of, for example, cobalt to be silicided is formed on the polycrystalline silicon film 24. Furthermore, as illustrated in FIG. 8E, a silicide film 31 is formed by heat treatment.
In this case, the silicide film 31 is likely to be broken at the location in which the interface 29a exists. However, it will be broken apart from the PN junction 29. This can suppress a significant increase in the resistance of the gate electrode.